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Renesas RZ/N2L-RSK

Introduction

Porting GOAL to Renesas RZ/N2L-RSK is in progress.

Information about the state of development, requirements, supported and upcoming features, resources and software handling are prospected in following chapters.

More information and documents are available at Renesas RZ/N2L-RSK.

Network protocols

The following network protocols are supported on RZ/N2L-RSK Arm® Cortex®-R52 single core.

• Profinet

• EtherNet/IP

• Modbus TCP/IP

• OPCUA

• CC-LINK IE Field Basic

• Powerlink

Upcoming network protocols.

• EtherCAT

• CC-LINK IE TSN

Please follow the links for detailed stack description.

In the first step of porting our network protocols to the new device, we focusing on single core solution only. Providing the multi-core versions of all network protocols is scheduled.

Features

• FreeRTOS Kernel V10.3.0

• Flexible Software Package (FSP) | Renesas

• Serial Interface for log messages

• 4 user LEDs (green, yellow + two red)

• 4 user DIP switches

• 2 user buttons

• support for storing CM variables remanent:

  • sflash via xSPI0

  • EEPORM via I2C

• booting GOAL application from xSPI0

Upcoming features:

• Micro Core To Core on shared memory for multi-core solutions

Components

LEDs

The user LEDs 0…3 are used by GOAL for visual interaction. They can be set by calling goal_targetSetLeds(). Reading the current LED state is possible by goal_targetGetLeds().

LEDs can also be accessed via GOAL LED API.

Memory

The general RZ/N2L memory map is shown in following table. The addresses indicates the maximal reserved memory.

Non-Volatile-Memory

Configuration or user data can be storage to nonvolatile memory. GOAL supports the following two different mediums on RZ/N2L RSK to keep information remanent. Both are accessed via GOAL media for nonvolatile storage.

sFlash

A 512 Mbit sflash is assembled at the RZ/N2L RSK and mapped to external address space xSPI0. The last 8kByte within this memory are reserved for CM storage by default.

EEPROM

This feature is disabled by default and not available in library demos.

GOAL CM variables are stored to EEPROM by setting compiler define GOAL_CONFIG_NVS_EEPROM_I2C to 1.

There are various limitations for this feature:

• EEPROM size is limited to 2kBytes on RSK board; but some GOAL projects (e.g. PNIO including SNMP and MRP) requiring 8kBytes and are consequently not supported.

• There is only a single EEPROM on RSK board available; this component is occupied by EtherCAT Slave Controler on EtherCAT projects and therefore not available for NVS.

• I2C module needs to be setup in 7-Bit address mode.

Open

Comparison of sFlash and EEPROM

Switches and buttons

The DIP switches SW3:1..SW3:4 and buttons SW1 & SW2 can be used as input signal to GOAL software. Their state is polled when calling goal_targetGetButtons(). The function returns the input state as a bit mask, which assign is specified in goal_target_board.h.

UART

UART0 is used by GOAL as serial interface for sending log messages or receiving Command line interface. The interface speed is 115200 by default.

Tracing

Data tracing is possible by GOAL API via following pins.

Tools

These software tools are required to run GOAL and its network protocol stacks on RZ/N2L-RSK. You may choose between e² studio or IAR Embedded Workbench.

• IAR Embedded Workbench Version 9.30.1 + RZ/N2L FSP Smart Configurator v1.2.0

• FSP with e² studio Installer v1.2.0

Running a sample project

Handling a sample project on RZ/N2L-RSK is described in following sections. This includes the process of loading software into RAM for debugging and flashing it to non-volatile storage.

Setup RZ/N2L-RSK

Before running a sample project on Renesas RZ/N2L-RSK, ensure to setup the board correctly. This chapter summary most important components, which are used by GOAL. A detailed explanation of each unit is available in Renesas Starter Kit+ for RZ/N2L User’s Manual at Renesas RZ/N2L-RSK.

All important components for handling GOAL on RZ/N2L-RSK are marked below.

The following configuration is used as default.

• plug USB to Serial Port for serial communication

  • After powering on the board, check the hardware manager for the assigned COM interface.

  • The interface speed is 115200 by default.

• plug DC Power In (USB Type-C) for power supply

• plug ETH0..ETH2 for network communication

Board components are designed and configured by Flexible Software Package (FSP) | Renesas Smart Configurator. The tool generates the source files of low level drivers, which are used by GOAL.

RZ/N2L-RSK with IAR Workbench

GOAL example projects for IAR Workbench is located at projects/<protocol>/<application>/iar/renesas/rzn2l_rsk*/rzn2l_rsk*.eww.

Before first use, the Smart Configurator needs to be added as external tool in IAR Workbench once by following steps:

• open IAR Workbench IDE and select Tools → Configure Tools…

• add a new tool by choosing New and enter the following properties

  • Menu Text: FSP Smart Configurator

  • Command¹: C:\Renesas\fsp_sc\eclipse\rasc.exe
    ¹: Absolute path to the Flexible Software Package Smart Configurator

  • Argument: --compiler IAR configuration.xml

  • Initial Directory: $PROJ_DIR$

Setup Board for debugger as followed.

• connect I-Jet to external debugger (MIPI-20) Connector

• short J9 for usage of external debugger

Flexible Software Package in FSP Smart Configurator

Flexible Software Package is used for board configuration. Each GOAL project is preconfigured for RZ/N2L-RSK. The files must be generated manually before building IAR projects. Customer’s modification by FSP Smart Configurator is possible.

• open an example projects in IAR Workbench (see section below for project import description).

• choose a Workspace from the selector or via context menu → Set as Active

  • rzn2l_rsk_ram - Single-Core for Debug

  • rzn2l_rsk_bootloader - Bootloader-ROM for flashing

• select Tools → FSP Smart Configurator from the menu to open Flexible Software Package (FSP) | Renesas

  • (optional) choose device family: Renesas RZ/N

  • a preconfigured project for the Smart Configurator is loaded and ready to use

• press Generate Project Content to generate FSP sources

Debugging RZ/N2L-RSK with IAR Workbench

• setup board

• open an example projects in IAR Workbench

• select Workspace rzn2l_rsk_ram - Single-Core

• generate project content with FSP Smart Configurator (see section above)

• select Project → Rebuild All to build the project

• power up the board

• press S3 to reset the board

• select Project → Download and Debug to download the project into RAM and start the debug session

Flashing RZ/N2L-RSK with IAR Workbench

• setup board

• open an example projects in IAR Workbench

• build RAM binary (see section above)

• select Workspace rzn2l_rsk_bootloader - Bootloader-ROM

• generate project content with FSP Smart Configurator (see section above)

• select Project → Rebuild All to compile the project

• power up the board

• select Project → Download → Download active application to flash the second stage bootloader and RAM binary into xSPI0
  Source and destination sections are defined in the linker file.

• press S3 to reset the board

When the device is powered up, the bootloader switches LED0 on to indicate application program copy start. After GOAL has been copied from xSPI0 flash to RAM, LED1 indicates application program copy end.

Debugging the second stage bootloader and its RAM binary is possible. But debug information of sflash’s RAM binary have to be included first. Therefore, open options of Bootloader workspace via Project → Options. Navigate to Debugger → Images and check the first box to Download extra image. Note, that Debug info only is enabled.

RZ/N2L-RSK with e²studio

GOAL example projects for e²studio is located at projects/<protocol>/<application>/e2studio/renesas/rzn2l_rsk*/

Setup Board by debugger as followed.

• connect Mico-USB to internal debugger (Micro-USB) connector J10

• open J9 for usage of internal debugger

Flexible Software Package in e²studio

Flexible Software Package is used for board configuration. Each GOAL project is preconfigured for RZ/N2L-RSK. The files will be generated on build automatically. Customer’s modification is possible by following steps.

• Open configuration.xml located at the project root (see section below for project import description).

• The preconfiguration for the FSP Configuration is loaded and ready to use.

• Press Generate Project Content to generate the FSP sources after modifications.

Note: There is a “FSP configuration” perspective available in e²studio. It can be enabled by Window → Perspective → Open Perspective → Other… and selecting FSP Configuration.

Debugging RZ/N2L-RSK with e²studio

• setup board

• open e²studio for RZ/N2L

• importing a new project is possible by selecting File → Import and choosing Existing Project into Workspace.

• Select root directory and Browse… into sub-directory projects of goal. All e²studio projects are listed and can be selected or deselected for import. Choose at least the *_ram version. Even if the *_bootloader version is not required for debugging, it is recommended to select it too in case the firmware should be flashed later on. Confirm by Finish.

• Optional: configuring board by FSP Configuration

• select the (in ram) project at Project Explorer and choose Project → Build Project. FSP sources are generated and project is build.

• click the bug symbol at the upper right corner while (in ram) project is highlighted to start debug session.

Flashing RZ/N2L-RSK with e²studio

• setup board

• open e²studio for RZ/N2L

• importing a new project is possible by selecting File → Import and choosing Existing Project into Workspace.

• Select root directory and Browse… into sub-directory projects of goal. All e2studio projects are listed and can be selected or deselected for import. Choose *_ram and *_bootloader version of the project. Confirm by Finish.

• Optional: configuring board by FSP Configuration

• select the (in ram) project at Project Explorer and choose Project → Build Project. FSP sources are generated and project is build.

• select the (in bootloader) project at Project Explorer and choose Project → Build Project. FSP sources are generated and project is build including the RAM binary.

• power up the board

• click the bug symbol at the upper right corner while (in bootloader) project is highlighted to flash the target and start debugging the bootloader.

When the device is powered up, the bootloader switches LED0 on to indicate application program copy start. After GOAL has been copied from xSPI0 flash to RAM, LED3 indicates application program copy end.

Downloads

GOAL Profinet Demo

A Profinet Demo is available by following download. The ZIP includes a 1h time limited, full feature protocol stack library, next to some basic (00410) and web-server (goal_http) examples.

The GSDML is located in protos/pnio/gsdml.

All projects are created for Renesas RZ/N2L-RSK. The board configuration is fixed in library projects and can not be modified by FSP SC.

Stack documentation and a Quick Start Guide is available at Documents & Manuals.

The software is under development and purposed for validation only.

>> download Profinet Demo for RZ/N2L-RSK (Date of update: 24.05.2024)

GOAL Ethernet/IP Demo

A EtherNet/IP Demo is available by following download. The ZIP includes a 1h time limited, full feature protocol stack, next to some basic (00410) and web-server (goal_http) examples.

The soc device description is located in application sub-directory at appl/goal_eip/.

All projects are created for Renesas RZ/N2L-RSK. The board configuration is fixed in library projects and can not be modified by FSP SC.

Stack documentation and a Quick Start Guide is available at Documents & Manuals.

The software is under development and purposed for validation only.

>> download Ethernet/IP Demo for RZ/N2L-RSK (Date of update: 24.05.2024)

GOAL Modbus/TCP

The Modbus TCP/IP Software is available by following download.

All projects are created for Renesas RZ/N2L-RSK.

Application description is available at Application Examples.

>> download Modbus/TCP for RZ/N2L-RSK (Date of update: 24.05.2024)

GOAL OPC-UA Demo

A OPC-UA Demo is available by following download. The ZIP includes a 1h time limited, full feature protocol stack, next to some basic (00410) and web-server (goal_http) examples.

The soc device description is located in application sub-directory at appl/goal_opcua/.

All projects are created for Renesas RZ/N2L-RSK. The board configuration is fixed in library projects and can not be modified by FSP SC.

Stack documentation and a Quick Start Guide is available at Documents & Manuals.

The software is under development and purposed for validation only.

>> download OPC-UA for RZ/N2L-RSK (Date of update: 24.05.2024)

GOAL Powerlink Demo

A Powerlink Demo is available by following download. The ZIP includes a 1h time limited, full feature protocol stack, next to some basic (00410) and web-server (goal_http) examples.

All projects are created for Renesas RZ/N2L-RSK.

>> download Powerlink for RZ/N2L-RSK (Date of update: 24.05.2024)

Known issues

USB-Device could not be detected

• power off the device

• unplug external debugger and UART to serial port on PC side

• power on the device

• plug the external debugger and UART to serial port

Software development is still in progress. If any further issues are detected, please contact us.

In case of any specific questions, you can contact our support team via support@port.de.

You are interested in other protocols for this device? Please contact the sales team for commercial questions via service@port.de.

May 22, 2024