Introduction

POWERLINK is supported for single and multi-core usage on RZ/N1D, RZ/N1S and RZ/N1L devices.
The stack protocol runs on Cortex-M3 in both variants and features hardware support by frame pattern detection and automatic response transmission for short response delays.

In multi-core variant the user application is executed on a separate core. For RZ/N1D and RZ/N1S its the on-chip Cortex-A7 which features Linux for D-model and ThreadX for S-Model. The L-Model can be connected to any external chip via SPI, for example the Synergy S7GS-SK.

Hardware

The Renesas RZ/N-YConnect-It controllers have been used for development and testing.

Known Restriction

The board needs to be used as single port device in a POWERLINK network. For that, ETH5 is prioritized.