TI TMS320F2838x

Owned by Jörg Schumann
Last updated: May 31, 2021 by Michael Struwe
3 min read

Introduction

This document describes the integration of the delivered EtherCAT example projects for TI TMS320F28388D target with the development environment TI Code Composer Studio.

Target System

The port EtherCAT stack is implemented and tested with TI TMDSCNCD28388D (F28388D controlCARD evaluation module) put on HSEC180 controlCARD Baseboard Docking Station.

Toolchain:

Compiler/IDE: Code Composer Studio v9.3 (or newer)
Flash tool/Debugger: Onboard TI XDS100v2 USB Debug Probe

General information

The TMS320F28388D is a multicore CPU. The EtherCAT Stack runs on Cortex-M4 core CM (Connectivity Manager). The chip’s internal EtherCAT controller is connected to the CPU via the memory bus (16bit memory access).
The EtherCAT driver and examples use TI Software SDK TI C2000ware + Motor Control SDK. This package is available from TI web: C2000WARE-MOTORCONTROL-SDK Software development kit (SDK) | TI.com

You can find port’s EtherCAT example projects in the folder of the delivery package:

../examples/ti_tms320f2838x/

Before you can run the EtherCAT Stack you must load a suitable SW project on Master CPU1 (C28x DSP core).
For a quick start you can use the TI example "f2838x_cpu1_allocate_ecat_to_cm" from the TI Software SDK / C2000ware.

Import projects

TI example "f2838x_cpu1_allocate_ecat_to_cm" for Master CPU1:

The search path shows the default path in the installed TI C2000ware/Motor Control SDK.

Import the delivered EtherCAT example project from port for CPU core “Conectivity manager” (CM):

The port Code Composer Studio project contains different examples.

You can select the desired sample application by activating the corresponding “Build Configuration”:
”Project --> Build Configurations --> Set Active --> XXX”

alternatively: “Project --> Build Configurations --> Manage”

Now you can build both projects.

If both builds were successful you can load and run the binaries in the CPU cores:

First "f2838x_cpu1_allocate_ecat_to_cm" to CPU1 core.

Second, the EtherCAT example from port to “CM” CPU core (Cortex-M4):

Available sample applications

  • s01_tms320f28388x:

    • SDO read and write

    • 2 RX-PDOs and 2 TX-PDOs

    • object dictionary containing objects of various data types

  • s01_tms320f28388x_cia401

    • EtherCAT slave with CiA 401 profile example application

  • s03_tms320f28388x:

    • SDO read and write

    • SDO Info service

    • SDO Info object names

    • 2 RX-PDOs and 2 TX-PDOs

    • Split SDO-Access

    • Split NMT-Control

    • object dictionary containing objects of various data types

  • s04_tms320f28388x:

    • SDO read and write

    • SDO Info service

    • SDO Info object names

    • 2 RX-PDOs and 2 TX-PDOs

    • Split SDO-Access

    • Split NMT-Control

    • object dictionary containing objects of various data types

    • EoE service with rudimentary ARP and IGMP support (ping)

    • FoE service

  • s05_tms320f28388x:

    • SDO read and write

    • SDO Info service

    • SDO Info object names

    • 2 RX-PDOs and 2 TX-PDOs

    • object dictionary containing objects of various data types

    • virtual objects

  • s07_tms320f28388x:

    • SDO read and write

    • SDO Info service

    • SDO Info object names

    • 2 RX-PDOs and 2 TX-PDOs

    • object dictionary containing objects of various data types

    • FoE mailbox service

    • BOOTSTRAP NMT mode

  • s09_tms320f28388x:

    • SDO read and write

    • 2 RX-PDOs and 2 TX-PDOs

    • object dictionary containing objects of various data types

    • dynamic PDO mapping with extension module usr_dynPdoMapping

  • s10_tms320f28388x_xxx:

    • Interrupt handling

    • xxx = isr: PDI Events are handled in an ISR

    • xxx = isr_dc: PDI Events and DC Events are handled in separate ISRs

  • s11_tms320f28388x_cia402

    • EtherCAT slave with CiA 402 profile example application