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Renesas RZ/N2L-EU140

Introduction

Porting GOAL to Renesas RZ/N2L-EU140 is in progress.

Information about the state of development, requirements, supported and upcoming features, resources and software handling are prospected in following chapters.

More information and documents are available at Renesas RZ/N2L-EU140.

Network protocols

The following network protocols are supported on RZ/N2L-EU140 Arm® Cortex®-R52 single core.

• Profinet

• EtherNet/IP

• Modbus TCP/IP

• OPCUA

• CC-LINK IE Field Basic

• CC-LINK IE TSN

• Powerlink

• CANopen

Upcoming network protocols.

• EtherCAT

Please follow the links for detailed stack description.

In the first step of porting our network protocols to the new device, we focusing on single core solution only. Providing the multi-core versions of all network protocols is scheduled.

Features

• FreeRTOS Kernel V10.3.0

• Flexible Software Package (FSP) | Renesas v2.0.0

• Serial Peripheral Interface

• 15 user LEDs

• 16 user DIP switches

• support for storing CM variables remanent:

  • sflash via xSPI0

  • EEPORM via I2C

• CAN controller access

• second stage bootloder for starting GOAL application from xSPI0

Components

LEDs

The user LEDs 0…14 are used by GOAL for visual interaction. They can be set by calling goal_targetSetLeds(). Reading the current LED state is possible by goal_targetGetLeds().

LEDs can also be accessed via GOAL LED API.

Memory

The general RZ/N2L memory map is shown in following table. The addresses indicates the maximal reserved memory.

Non-Volatile-Memory

Configuration or user data can be storage to nonvolatile memory. GOAL supports the following two different mediums on RZ/N2L-EU140 to keep information remanent. Both are accessed via GOAL media for nonvolatile storage.

sFlash

A 512 Mbit sflash is assembled at the RZ/N2L-EU140 and mapped to external address space xSPI0. The last 8kByte within this memory are reserved for CM storage by default.

EEPROM

This feature is disabled by default and not available in library demos.

GOAL CM variables are stored to EEPROM by setting compiler define GOAL_CONFIG_NVS_EEPROM_I2C to 1.

This is possible via IDE project properties.

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GOAL_CONFIG_NVS_EEPROM_I2C define at E2Studio

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GOAL_CONFIG_NVS_EEPROM_I2C define at IAR Workbench

There are various limitations for this feature:

• EEPROM size is limited to 2kBytes on EU140 board; but some GOAL projects (e.g. PNIO including SNMP and MRP) requiring 8kBytes and are consequently not supported.

• There is only a single EEPROM on EU140 board available; this component is occupied by EtherCAT Slave Controler on EtherCAT projects and therefore not available for NVS.

• I2C module needs to be setup in 7-Bit address mode.

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Switches and buttons

The DIP switches J6 and J7 can be used as input signal to GOAL software. Their state is polled when calling goal_targetGetButtons(). The function returns the input state as a bit mask, which assign is specified in goal_target_board.h.

Tools

These software tools are required to run GOAL and its network protocol stacks on RZ/N2L-EU140. You may choose between e² studio or IAR Embedded Workbench.

• IAR Embedded Workbench Version 9.30.1 + RZ/N2L FSP Smart Configurator v2.0.0

• FSP with e² studio Installer v2.0.0

• Python and python intelhex library for creating firmware

Running a sample project

Handling a sample project on RZ/N2L-EU140 is described in following sections. This includes the process of loading software into RAM for debugging and flashing it to non-volatile storage.

Setup RZ/N2L-EU140

Before running a sample project on Renesas RZ/N2L-EU140, ensure to setup the board correctly. This chapter summary most important components, which are used by GOAL. A detailed explanation of each unit is available in Renesas Starter Kit+ for RZ/N2L User’s Manual at Renesas RZ/N2L-EU140.

All important components for handling GOAL on RZ/N2L-EU140 are marked below.

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key components for GOAL on RZ/N2L-EU140

The following configuration is used as default.

• plug J5 for power supply

• plug ETH0..ETH2 for network communication

Board components are designed and configured by Flexible Software Package (FSP) | Renesas Smart Configurator. The tool generates the source files of low level drivers, which are used by GOAL.

Second stage bootloader

The RZ/N2L-EU140 offers a Boot Function, which loads a program from flash to BTCM and execute it. Due to the size limitation of 120KB it is usable for very small applications only. More details about the RZ/N2L Boot Function are available at Renesas Document RZ/N2L Group User’s Manual: Hardware - Chapter “Operating Mode Descriptions”.

Handling applications larger than 120KB requiring a second stage bootloader, that copies the GOAL image from flash to System RAM and executes it there.

When the device is powered up, the second stage bootloader is loaded from flash into BTCM by Boot Function. The following steps are then performed.

1. Starting second stage bootloader

2. validating GOAL firmware image on flash and copy it into RAM.

3. End of second stage bootloader

RZ/N2L-EU140 with IAR Workbench

GOAL example projects for IAR Workbench are located at projects/<protocol>/<application>/iar/renesas/rzn2l_eu140*/rzn2l_eu140*.eww.

Adding FSP Smart Configurator to IAR Workbench

Before first use, the Smart Configurator needs to be added as external tool in IAR Workbench once by following steps:

• open IAR Workbench IDE and select Tools → Configure Tools…

• add a new tool by choosing New and enter the following properties

  • Menu Text: FSP Smart Configurator

  • Command¹: C:\Renesas\fsp_sc\eclipse\rasc.exe
    ¹: Absolute path to the Flexible Software Package Smart Configurator

  • Argument: --compiler IAR configuration.xml

  • Initial Directory: $PROJ_DIR$

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setup FSP Smart Configurator Tool in IAR Workbench IDE

Setup Board for debugger as followed.

• connect I-Jet to external debugger (MIPI-10) Connector

• short J3 for usage of external debugger

Code generation by FSP Smart Configurator

The FSP Smart Configurator is used for board setup. Each GOAL project is preconfigured for RZ/N2L-EU140. The driver files and configuration files must be generated manually before building IAR projects, otherwise it will fail. Customer’s modification by FSP Smart Configurator is possible.

• open an example projects in IAR Workbench (see section below for project import description).

• choose a Workspace from the selector or via context menu → Set as Active

  • *_ram - Debug: RAM configuration of the application

    *_ram - Release: xspi0 configuration of the application

  • *_bootloader - xspi0: second stage bootloader for starting any application from qSPI0 flash

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selecting workspace

• select Tools → FSP Smart Configurator from the menu to open Flexible Software Package (FSP) | Renesas

  • (optional) choose device family: Renesas RZ/N

  • a preconfigured project for the Smart Configurator is loaded and ready to use

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FSP Smart Configurator

• press Generate Project Content to generate FSP sources

Debugging GOAL application on RZ/N2L-EU140 with IAR Workbench

• setup board

• Short J3 for external Debugger

• Connect I-Jet to External Debugger Connector

• open an example projects in IAR Workbench

• select Workspace: *_ram - Debug

• open and generate board by FSP Configuration as described in section Flexible Software Package in FSP Smart Configurator

• select Project → Rebuild All to build the project

• select Project → Download and Debug to download the project into RAM and start the debug session

Flashing second stage bootloader to RZ/N2L-EU140 with IAR Workbench

• setup board

• Short J3 for external Debugger

• Connect I-Jet to External Debugger Connector

• open an example projects in IAR Workbench

• select Workspace: *_bootloader - xspi0

• open and generate board by FSP Configuration as described in section Flexible Software Package in FSP Smart Configurator

• select Project → Rebuild All to build the project

• select Project → Download and Debug to download the project into qSPI0 and start the debug session

Flashing GOAL to RZ/N2L-EU140 with IAR Workbench

• ensure that the second stage bootloader has been flashed

• setup board

• connect I-Jet to External Debugger Connector

• open an example projects in IAR Workbench

• select Workspace: *_ram - Release

• open and generate board by FSP Configuration as described in section Flexible Software Package in FSP Smart Configurator

• select Project → Rebuild All to build the project

• select Project → Downlaad → Download file...

• navigate into the IAR project directory, open the subfolder Release/Exe and select All Files (*.*)

• choose the firmware hex file *.qspi.fw.hex and confirm for downloading the file into flash

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GOAL qspi firmware hex file

• press S3 to reset the board

RZ/N2L-EU140 with e²studio

GOAL example projects for e²studio is located at projects/<protocol>/<application>/e2studio/renesas/rzn2l_eu140*/

Extend default board setup by debugger as followed.

• connect Mico-USB to internal debugger (Micro-USB) connector J5

• open J3 for usage of internal debugger

Import GOAL projects into e²studio

• open e²studio for RZ/N2L

• importing a new project is possible by selecting File → Import and choosing Existing Project into Workspace.

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import assistant (1)

• Select root directory and Browse… into sub-directory projects of goal. All e²studio projects are listed and can be selected or deselected for import.

  • *_bootloader: second stage bootloader for starting any application from qSPI0 flash

  • *_ram: debug and release configuration of the application

• Choose the *_ram and at least one *_bootloader project. Confirm by Finish.

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import assistant (2)

Flexible Software Package in e²studio

Flexible Software Package is used for board configuration. Each GOAL project is preconfigured for RZ/N2L-EU140. Driver and configuration files will be generated on build automatically. Customer’s modification is possible by following steps.

• Open configuration.xml located at the project root (see section below for project import description).

• The preconfiguration for the FSP Configuration is loaded and ready to use.

• Press Generate Project Content to generate the FSP sources after modifications.

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generating FSP project content in e²studio

Note: There is a “FSP configuration” perspective available in e²studio. It can be enabled by Window → Perspective → Open Perspective → Other… and selecting FSP Configuration.

Debugging GOAL application on RZ/N2L-EU140 with e²studio

• import GOAL project as described in section Import GOAL projects into e2studio

• (optional) configuring board by FSP Configuration as described in section Flexible Software Package in e2studio

• select *_ram (in ram) project at Project Explorer

• choose Debug configuration by Project → Build Configurations → Set Active → Debug

• select Project → Build Project. FSP sources are generated and project is build.

• navigate to Run → Debug configurations.. and select the Renesas GDB Hardware Debugging *_ram Debug

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choosing application Debug configuration

• click Debug to start the debug session

Flashing second stage bootloader to RZ/N2L-EU140 with e²studio

GOAL Release configurations get only started if the second stage bootloader has been flashed once to the target.

• import GOAL project as described in section Import GOAL projects into e2studio

• select *_bootloader (in bootloader) project at Project Explorer

• select Project → Build Project. FSP sources are generated and project is build.

• navigate to Run → Debug configurations.. and select the Renesas GDB Hardware Debugging *_bootloader Release (xSPI0)

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choosing bootloader Release configuration

• click Debug to download the second stage bootloader

Flashing GOAL application to RZ/N2L-EU140 with e²studio

The Release configuration creates a firmware-hex file from binary image, which can be flashed by e²studio. Python and python intelhex library are required for this process.

• import GOAL project as described in section Import GOAL projects into e2studio

• (optional) configuring board by FSP Configuration as described in section Flexible Software Package in e2studio

• select *_ram (in ram) project at Project Explorer

• choose Release configuration by Project → Build Configurations → Set Active → Release

• select Project → Build Project. FSP sources are generated and project is build.

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• navigate to Run → Debug configurations.. and select the Renesas GDB Hardware Debugging *_ram Release (xSPI0)

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choosing application Release configuration

• click Debug to start the session

• open context menu of download symbol (see picture below) and select the *_qspi.fw.hex [Image only, 0x0].

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• download is initiate afterwards automatically

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Downloads

GOAL Profinet Demo

A Profinet Demo will be available soon by following download.

The ZIP includes a 1h time limited, full feature protocol stack with multiple example applications.

The GSDML is located in protos/pnio/gsdml.

All projects are created for Renesas RZ/N2L-EU140. The board configuration is fixed in library projects and can not be modified by FSP SC.

Stack documentation and a Quick Start Guide is available at Documents & Manuals.

The software is under development and purposed for validation only.

GOAL Ethernet/IP Demo

A EtherNet/IP Demo will be available soon by following download.

The ZIP includes a 1h time limited, full feature protocol stack with multiple example applications.

The soc device description is located in application sub-directory at appl/goal_eip/.

All projects are created for Renesas RZ/N2L-EU140. The board configuration is fixed in library projects and can not be modified by FSP SC.

Stack documentation and a Quick Start Guide is available at Documents & Manuals.

The software is under development and purposed for validation only.

GOAL Modbus/TCP

GOAL OPC-UA Demo

A OPC-UA Demo will be available soon by following download.

The ZIP includes a 1h time limited, full feature protocol stack with multiple example applications.

The soc device description is located in application sub-directory at appl/goal_opcua/.

All projects are created for Renesas RZ/N2L-EU140. The board configuration is fixed in library projects and can not be modified by FSP SC.

Stack documentation and a Quick Start Guide is available at Documents & Manuals.

The software is under development and purposed for validation only.