In following sections are information provided about how to setup Renesas RZ/N1 boards for debugging and flashing the GOAL software.
Further documents about handling the platforms are released by Renesas at the Connect IT! DVD or in the download sections of RZ/N1D, RZ/N1S, RZ/N1L.
Please make sure that the following components are installed on the computer.
Table: Development Tools required by RZ/N1
Tool | Version |
IAR Embedded Workbench for ARM | 9.20.2 |
IAR C/C++ Compiler for ARM | 9.20.2 |
GCC | 8.2.0 |
dfu-util/ dfu_prog (from YCONNECT-IT) |
GCC v8.2.0 is available in Ubuntu 18.04, for example.
Optional software is not urgently but recommended for facilitated development.
Terminal Emulator: Log messages will be printed to the UART of the CPU Board.
Please take care to follow the setup guidelines for the RZ/N1 Demo Board from the YCONNECT IT! Quick Start Guide.
Please follow these initial steps to setup the UART and DFU connection.
Connect the board to a PC via the UART and the DFU interface. After the driver for the device has been installed, additional serial ports will show up.
On Linux PCs, if you have no other serial-over-USB devices attached, this is /dev/ttyUSB2.
On Windows PCs, open the device manager and look up for new USB Serial Ports on section ports. The RZ/N1D and RZ/N1S board uses the 3rd of the 4 COM ports.
Open and configure a suitable terminal emulator. The baud rate of the serial interface is 115200.
On Linux PCs, open a serial terminal e.g. with cu -e -o -115200 -l /dev/XXX. Replace the XXX with the serial device where the UART of the board is connected to.
On Windows PCs, open a serial terminal program e.g. PuTTY and select the COM port where the UART is connected to.
The following RZ/N1 hardware revisions has been used for GOAL development.
Name | Hardware-ID | Version |
|---|---|---|
RZ/N1D | EESS-0401-130-04 | v4.30 |
RZ/N1S | EESS-0401-141-02 | v4.10 |
RZ/N1L | EESS-0401-155-01 | v2.00 |
RZ/N1-EB | EESS-0401-131-03 | v2.00 |
The initial setup of the hardware and loading of the Cortex-M3 firmware from flash is done by U-Boot bootloader on RZ/N1D and RZ/N1S. Additionally, U-Boot starts Linux respectively ThreadX on Cortex-A7 when running the boards in multicore. The RZ/N1L is working without any bootloader.
If no bootloader was yet installed on RZ/N1D or RZ/N1S please refer to the board YCONNECT IT! Quick Start Guide.
There are many similarities between the derivatives of the RZ/N1 series but some minor differences, too. Therefore, this section describes how to flash the GOAL software to the board and how a debug session is initiated.
All standalone projects and the CC project of the Core To Core variant contain different workspaces for each board variant. The project workspaces ending on *_eb contain the configuration for the CPU board together with the extension board. The other project workspaces contain the configuration for working with the CPU board only.
Additionally, the release provides the standalone projects as library version. The applicable project directories are ending on *_lib, like goal\projects\goal_eip_rpc_lib\, containing the sample projects, next to the library in the board specific subfolder of 00_lib.
Handling a standalone application on RZ/N1D or RZ/N1S is described in following sections. This includes the process of loading software into RAM for debugging and flashing it to non-volatile storage.
It is possible to load the code via debugger into RAM, which is a very fast approach to test the user application. To compile and load a project, follow these steps.
Start the IAR Workbench IDE.
Open a project by File → Open Workspace.
Figure: IAR Workbench IDE - Open Workspace
Go to the workspace folder and open it. In case the CPU board is used together with the extension board, please ensure to select the correct IAR-project.
Compile the project by Project → Compile or Project → Rebuild all.
Power up the device.
Open a serial terminal according as described in https://portgmbh.atlassian.net/wiki/spaces/GOALR/pages/257097731#Setup-terminal-interface.
Press any key on your keyboard to interrupt the bootloader.
Ensure to configure the U-Boot boot command to release the Cortex-M3 core after reset. This is done by the command:
setenv bootcmd "mw 0x04000004 1 && rzn1_start_cm3 && loop 0 1"
followed by
saveenv
and reset the board.
Connect the debugger to the system via the Download and Debug button of the IAR Workbench.
Figure: Download and Debug button
After the Debug view opened, press F5 or click on the “Go” button.
The board uses the U-Boot bootloader for initial setup of the hardware and loading of the Cortex-M3 firmware. This chapter describes how to install the compiled Cortex-M3 software on the flash of the board. If no bootloader was yet installed, please refer to the board specific YCONNECT IT! Quick Start Guide.
Connect a PC.
Power up the board.
Open a serial terminal according as described in https://portgmbh.atlassian.net/wiki/spaces/GOALR/pages/257097731#Setup-terminal-interface.
Hit any key to stop the autoboot of the U-Boot.
Type dfu in the serial terminal of the board and hit enter.
Use the device Firmware Update (dfu) on your PC to download the binary file into the DFU interface named sf_cm3.
Linux:
On a terminal start the command
sudo dfu-util -a “sf_cm3” -D <FIRMWARE.bin>
Replace <FIRMWARE.bin> with the file name of the software to install. The binary is placed at the subfolder Debug-RAM\Exe of the IAR project folder.
Windows:
Start the dfu-prog located at Tools\dfu-util\dfu_prog\dfu_prog.exe of the YCONNECT IT! package.
Select Flash CM3 binary file to QSPI from the drop-down-menu and choose the <FIRMWARE.bin> of the software to install. The binary is placed at the subfolder Debug-RAM\Exe of the IAR project folder.
Afterwards, hit the button Execute cmd
When the download process is complete, press Ctrl+C on U-Boot.
Set the boot command bootcmd in the U-Boot:
setenv bootcmd "sf probe && sf read 0x4000000 d0000 90000 && rzn1_start_cm3 && loop 0 1"
Save the command to the flash:
saveenv
10. Reset the device
The RZ/N1L does not use any bootloaders. If any application is stored in flash, it will be started automatically. Both, loading into RAM and flash can be done using IAR workbench.
Start the IAR Workbench IDE.
Open a project via File → Open Workspace.
Go to the workspace folder and open it.
Compile the project via Project → Compile or Project → Rebuild all.
Power up the device.
Open a serial terminal according as described in https://portgmbh.atlassian.net/wiki/spaces/GOALR/pages/257097731#Setup-terminal-interface.
Choose either the Debug-RAM or the Debug-ROM configuration. First is used for debugging via IAR, second is loading the application into the flash.
Figure: IAR Configurations RAM and ROM for RZ/N1L
Follow these steps for the Debug-RAM configuration
Compile the project via Project → Compile or Project → Rebuild all.
Press and hold the devices software-reset button.
Click Download and Debug and release the software-reset button as soon as the “Busy” window opens.
Figure: IAR Workbench "Busy"-Window
Follow these steps for the Debug-ROM configuration
Click on Download and Debug.
Set reset mode to “Hardware” and press Make & Restart Debugger.
Check, if the reset mode is still on “Hardware”. If not, repeat the previous step.
Figure: Changing Reset mode of RZ/N1L in Debug-ROM configuration
After the Debug view opened, click on the “Go” button.
Handling a multicore application on RZ/N1D is described in following sections. This includes the process of loading software into RAM for debugging and flashing it to non-volatile storage.
The multicore project of the communication core is located in the board specific subdirectory of the protocol stack projects\**\00_goal_rpc_demo\1.
Load the Cortex-M3 binary file to the flash according to the steps 1-7 described in https://portgmbh.atlassian.net/wiki/spaces/GOALR/pages/257097731#Flashing-Cortex-M3-Software-%E2%80%93-RZ%2FN1D-and-RZ%2FN1S and continue by following points.
Set the boot command bootcmd in the U-Boot for loading Cortex-M3 and Cortex-A7 images and booting both with a delay of 4 seconds:
setenv bootcmd "sf probe && sf read 0x4000000 d0000 90000 && sf read 0x8ffe0000 b0000 20000 && sf read 0x80008000 1d0000 f00000 && rzn1_start_cm3 && sleep 4 && bootm 0x80008000 - 0x8ffe0000"
Save the boot command to the flash saveenv
Reset the device
The user application runs on the Linux system of the Cortex A7. Its binary must be created by GCC and downloaded to the RZ/N board manually.
It is recommended to maintain a consistent boot order of the communication and the application core. Therefore, it is advised to always start the R-IN engine / Cortex-M3 (communication core) first and boot the Cortex-A7 (application core) after the communication core has finished its initialization. |
The following steps describe, how to build a binary and download it to the RZ/N1D board.
Navigate with the terminal of a Linux PC to the gcc directory of a project for the application core.
Start the build process by executing the Makefile by typing make
Choose the target platform “rzn1d_a7_linux”.
Power up the board and wait till Linux booted successfully.
Copy the created binary file projects/**/build/rzn1d_a7_linux/goal_rzn_a7_demo_board.bin1 to the RZ/N1 board by e.g. secure copy (scp).\
Copy the application corresponding library projects/*/00_lib/gcc/build/rzn1d_a7_linux/libgoal_rzn1d_a7_linux.so to the RZ/N1D board by e.g. secure copy (scp).
Start the binary file on the target by typing the commands
export LD_LIBRARY_PATH=.
./goal_rzn1d_a7_linux.bin –i eth0
GOAL setups the connection to the communication core via core to core and starts the user application. The initialization is done when the log message “GOAL initialized” is printed at the terminal, if logging is activated.
The Linux Kernel can start the user application on the Cortex-A7 automatically with the help of the start script S99goal_app.sh located at /etc/rc5.d/ on Cortex-A7. Please ensure, that goal_rzn1d_a7_linux.bin and its library is placed at /home/root/.
Disabling the start script is possible by adding the boot argument GOAL_APPL_LINUX_PREV.
Power up the board.
Hit any key to stop the autoboot of the U-Boot.
Add the boot argument for preventing the application autoboot by
setenv bootargs "${bootargs} GOAL_APPL_LINUX_PREV"
Save the command to the flash by:
saveenv
Reset the device.
Reenabling the start script is possible by deleting the boot argument GOAL_APPL_LINUX_PREV.
Power up the board.
Hit any key to stop the autoboot of the U-Boot.
Display the environment by
env print
The latest boot arguments are listed at the line bootargs=
Copy these arguments, except GOAL_APPL_LINUX_PREV and paste them at <paste> on the following command
setenv bootargs “<paste>”
Save the command to the flash by:
saveenv
Reset the device.
Handling a multicore application on RZ/N1S is described in following sections. This includes the process of loading software into RAM for debugging and flashing it to non-volatile storage.
Similar to the standalone variant the core to core variant is also capable to run from the RAM while debugging the application core and the communication core at the same time. The communication core software might be provided as demo binary only. In such a case, debugging is limited to the application core.
The IAR Embedded Workbench runs two instances of the IDE, one for each core, in a master-slave-system to share the access to the board keeping both instances synchronous.
The usage and setup of the multicore debugging will be exemplary described for the Simple IO example running on the application core under ThreadX using the Cortex-M3 for handling the network stack as the communication core.
It is recommended to maintain a consistent boot order of the communication and the application core. Therefore, it is advised to always start the R-IN engine / Cortex-M3 (communication core) first and boot the Cortex-A7 (application core) after the communication core has finished its initialization. |
To run the core to core variant of the Simple IO example please perform the following steps:
Open the AC IAR project workspace, e.g projects\goal_eip_rpc\opener\01_simple_io\iar\renesas\rzn1s_a7_threadx\rzn1s_a7_threadx.eww
Open the project options and navigate to the subcategory Debugger → Multicore.
Enable Multicore master mode and select the 00_goal_rpc_demo project as slave workspace to use. Please note, that the “slave project” and the “slave configuration” is already preconfigured for the GOAL slave projects.
The core to core variant requires the 00_goal_rpc_demo project running on the Cortex-M3. It can also be used for the other application core demo applications.
The slave workspace rzn1s_demo_board.eww for the example above is located in the following project directory projects\goal_eip_rpc\opener\00_goal_rpc_demo\iar\renesas\rzn1s_demo_board\.
Figure: Multicore Debug Option
When using the RZ/N1S expansion board, please ensure to select the correct CC project located at the projects rzn1s_demo_board_eb directory. Additionally, adjust the entry “Slave project” in the subcategory “Multicore” to rzn1s_demo_board_eb.
Compile the project via Project → Compile or Project → Rebuild all.
Press the Download and Debug button
This will cause IAR to open the slave workspace as an additional IAR workbench instance, builds the slave project and load both – the master and the slave project – to the board sharing the debugger.
When the software from both instances is loaded to the board and the IDE switches in the debug mode an additional dialog for multicore debugging is available giving the following options:
start all cores at once
stop all cores at once
toggle execution mode
Figure: Multicore Debug Interface
The binary of the Cortex-M3 communication core is located in the board specific subdirectory of projects\**\00_goal_rpc_demo\1. Load it to the flash according to the steps 1-7 described in https://portgmbh.atlassian.net/wiki/spaces/GOALR/pages/257097731#Flashing-Cortex-M3-Software-%E2%80%93-RZ%2FN1D-and-RZ%2FN1S.
The user application for Cortex-A7 is handled in a similar way. Choose a CC coresponding AC sample project and build the binary file with IAR workbench according to steps 1-4 described in https://portgmbh.atlassian.net/wiki/spaces/GOALR/pages/257097731#Standalone-Application---RZ%2FN1D-and-RZ%2FN1S.
Afterwards, the binary located in the subdirectory Debug\Exe can be flashed to the DFU interface named sf_kernel, according to the steps 1-7 described in https://portgmbh.atlassian.net/wiki/spaces/GOALR/pages/257097731#Flashing-Cortex-M3-Software-%E2%80%93-RZ%2FN1D-and-RZ%2FN1S.
The AC binary must be loaded into the DFU interface named sf_kernel on RZ/N1S. |
Finally, configure the boot command <bootcmd> in u-boot.
Connect a PC to the board.
Power up the board.
Open a serial terminal according as described in https://portgmbh.atlassian.net/wiki/spaces/GOALR/pages/257097731#Setup-terminal-interface.
Hit any key to stop the autoboot of the U-Boot.
Set the boot command <bootcmd> in the U-Boot for loading Cortex-M3 and Cortex-A7 images and booting both with a delay of 4 seconds:
setenv bootcmd "sf probe && sf read 0x4000000 d0000 80000 && dcache off && sf read 0x80008000 1d0000 600000 && rzn1_start_cm3 && sleep 1 && go 0x80008000"
Save the boot command to the flash:
saveenv
Reset the device
The binary file for the Cortex-M3 is located in the board type related IAR Embedded Workbench folder projects\**\00_goal_rpc_demo\1.
Please refer to https://portgmbh.atlassian.net/wiki/spaces/GOALR/pages/257097731#Standalone-Application---RZ%2FN1L for building and downloading the Core To Core variant on RZ/N1L. It is handled the same as the standalone variant.
For mulit core projects, the RZ/N1L is used as communication core, while the e.g. Synergy S7GS-SK is used as application core. Data exchanging is done by SPI. The boards are connected as followed.
Figure: SPI connection of Synergy S7GS-SK (left) and RZ/N1L (right)
Table: PINs for SPI usage
function | color | S7GS-SK | RZ/N1L |
GND | Black | J24-7 | CN20-5 |
SPI Clock | Green | J24-6 | CN20-4 |
MISO | Blue | J24-5 | CN20-3 |
MOSI | Yellow | J24-4 | CN20-2 |
SPI chip select | Red | J24-3 | CN20-1 |
Please note the synergy quick start guide for setup the named core. By default, the RZ/N1L uses the SPI channel 5 and the following GPIOs
Table: GPIOs for SPI usage
GPIO | Usage |
62 | SPI clock |
63 | MOSI |
64 | MISO |
65 | SPI chip select |
The board supports only SPI mode 1 and 3. Please set the SPI mode to 3 by defining
|
1 The symbol ** is used as wildcard. It includes all projects and their subdirectories.